SiFive expands its RISC-V Core range

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This article is part of TechXchange: RISC-V: The alternative to the instruction set

SiFive continues to release new versions of its RISC-V cores. Its two most recent additions include the Performance P550 core and the Performance P270 vector core, which target high performance computing applications. The P550 delivers a 2006 SPECInt score of 8.65 / GHz, comparable to other high-end application processors.

The company’s cores are supported by a range of silicon foundries as well as a number of FPGA platforms. One of the latest additions to the mix is ​​Intel’s foundry.

Amber Huffman, Intel Fellow and CTO of the IP Engineering Group at Intel, said: “We are delighted to be a Senior Development Partner with SiFive to show joint customers the impressive performance of their P550 on our Horse Creek platform. 7 nm. By combining advanced Intel interface IP such as DDR and PCIe with SiFive’s highest performing processor, Horse Creek will provide a valuable and scalable development vehicle for cutting-edge RISC-V applications.

The Performance P550 uses a 13-stage, triple-edited failed pipeline compatible with the RISC-V RV64GC ISA (Fig. 1). It is based on the SiFive U84 microarchitecture. Each core has its own L1 and L2 cache.

% {[ data-embed-type=”image” data-embed-id=”60dc832a2a3ece0f568b45eb” data-embed-element=”span” data-embed-size=”640w” data-embed-alt=”1. The P550 employs a triple-issue instruction queue with multiple ALUs.” data-embed-src=”https://img.electronicdesign.com/files/base/ebm/electronicdesign/image/2021/06/SiFive_Fig_1_web.60dc832933af1.png?auto=format&fit=max&w=1440″ data-embed-caption=”1. The P550 employs a triple-issue instruction queue with multiple ALUs.” ]}%

The P550 can be shipped in a cluster of up to four cores (Fig. 2). This quad-core complex uses roughly the same area of ​​silicon as an Arm Cortex-A75 core, providing a significant performance advantage per area. Keep in mind the look of the area.

% {[ data-embed-type=”image” data-embed-id=”60dc83adf3a390a3098b482a” data-embed-element=”span” data-embed-size=”640w” data-embed-alt=”2. P550 cores can be combined into a symmetrical multicore cluster.” data-embed-src=”https://img.electronicdesign.com/files/base/ebm/electronicdesign/image/2021/06/SiFive_Fig_2_web.60dc83ac8321a.png?auto=format&fit=max&w=1440″ data-embed-caption=”2. P550 cores can be combined into a symmetrical multicore cluster.” ]}%

The Performance P270 is built around a highly efficient, dual-problem, 8-stage tidy pipeline with a 256-bit vector unit (Fig. 3). It is compatible with the RISC-V RV64GCV ISA and can deliver a 2006 SPECInt score of 4.6 / GHz. While the P550 fits in 0.38mm2, the P270 only requires 0.175mm2. The P270 can also be arranged in a multi-core configuration.

% {[ data-embed-type=”image” data-embed-id=”60dc835654a18ea3158b480c” data-embed-element=”span” data-embed-size=”640w” data-embed-alt=”3. The P270 has an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA.” data-embed-src=”https://img.electronicdesign.com/files/base/ebm/electronicdesign/image/2021/06/SiFive_Fig_3_web.60dc835530d98.png?auto=format&fit=max&w=1440″ data-embed-caption=”3. The P270 has an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA.” ]}%

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